Integrated circuit (IC) chips include millions of transistors and other components fabricated on a substrate of semiconducting material such as silicon. The components are interconnected through lines of conductive material, most commonly aluminum. As IC chips increase in density and complexity, the dimensions of silicon features must be reduced in order to pack more components onto a single chip. One technical challenge in reducing feature size is maintaining adequate electrical connections between silicon features and the conductive lines. As the feature size decreases, the contact area between the metal and the silicon decreases, and thus, the contact resistance increases.
To provide more reliable contacts through smaller surface areas, certain metals such as refractory or near-noble metals may be used because they react with silicon to form silicides which create highly conductive and reliable contacts. A silicide contact is typically formed by depositing a thin layer of metal over silicon regions where contacts are to be formed, and then thermally treating it to cause the silicon and metal to react and form a silicide layer between the metal and silicon. Unreacted metal is removed, and the silicon features are then interconnected through conventional conductive lines which now contact the silicide layer rather than the silicon.
FIGS. 1-4 illustrate a prior art technique for forming silicide contacts. Referring to FIG. 1, a metal-oxide-semiconductor (MOS) transistor having a gate electrode 10 and source/drain regions 30 (also referred to as active regions) is first fabricated on a substrate 40 in a conventional manner. The gate electrode 10 includes a polysilicon gate layer 11, and a mask layer 13 which are stacked on top of an insulating layer 15 that covers the channel region of the substrate between the active regions 30. Spacers 20 are formed on the sidewalls of the gate electrode 10 and are typically used during the manufacturing process to provide accurate alignment of the active regions 30 with the sidewalls of the gate electrode 10. For example, the active regions 30 are typically heavily doped with impurities so that they are highly conductive. The sidewall spacers 20 facilitate the creation of lightly doped drain (LDD) regions in the portions of the active regions 30 that lie directly under the spacers. The LDDs tend to reduce the electric field strength and provide more accurate control of the impurity doping near the edges of the gate 10, both of which tend to critically effect the operation of the transistor.
Referring to FIG. 2, a dielectric layer 50 is deposited over the substrate, and then contact holes 51 are formed in the dielectric layer 50 to expose portions of the active regions 30. A thin layer of metal 60 is next deposited over the surface of the dielectric layer 50 as well as the exposed portions of the active regions 30. The entire device is then thermally treated to cause the metal at the bottom of the contact holes 51 to react with the silicon to form a silicide layer 70 as shown in FIG. 3. Unreacted metal is then removed, at least on the top of the dielectric layer 50, and interconnects are formed by depositing a layer of aluminum 80 in the contact holes 51 as shown in FIG. 4.
The characteristics of the silicide layer 70, e.g., thickness, resistance, and the like, may be controlled through various parameters such as the type of metal, annealing time and temperature, etc.
One particular problem with formation of a silicide layer is lateral growth of the silicide along the surface of the substrate. For example, encroachment of silicide under the sidewall spacers and even into the channel regions can result in increased leakage current and/or transistor failure. One prior art technique for preventing unwanted silicide encroachment involves implanting encroachment-inhibiting ions such as nitrogen into the active regions prior to thermal treatment.
Another problem is that certain transistors may be critical to the operating speed of the IC, and therefore may require thicker silicide contacts with lower resistance, while the vast majority of other transistors are less critical and only require thinner silicide contacts. A prior art technique provides thicker silicide layers for select transistors by using lower impurity doping concentrations in the active regions of the select transistors, while using higher concentrations for the active regions of other transistors.